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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . l i + c h a r g e r p r o t e c t i o n i c w i t h i n t e g r a t e d p - m o s f e t input over-voltage protection input over-current protection battery over-voltage protection high immunity of false triggering high accuracy protection threshold a built-in p-mosfet thermal shutdown protection available in a tdfn2x2-8 package lead free and green devices available (rohs compliant) f e a t u r e s a p p l i c a t i o n s cell phones g e n e r a l d e s c r i p t i o n s i m p l i f i e d a p p l i c a t i o n c i r c u i t the apl3215/a provides complete li+ charger protection against input over-voltage, input over-current, and battery over-voltage. when any of the monitored parameters are over the threshold, the ic removes the power from the charging system by turning off an internal switch. all pro- tections also have deglitch time against false triggering due to voltage spikes or current transients. the apl3215/a integrates a p-mosfet with the body di- ode reverse protection to replace the external p-mosfet and schottky diode for charger function of cell phone?s pmic. when the chrin voltage drops below v bat +20mv, the internal power select circuit will reverse the body diode?s terminal to prevent a reverse current flowing from the battery back to chrin pin. the apl3215/a provides complete li+ charger protec- tions and saves the external mosfet and schottky diode for the charger of cell phone?s pmic. the above features and small package make the apl3215/a an ideal part for cell phones applications. p i n c o n f i g u r a t i o n acin 1 acin 2 vbat 4 5 gatdrv gnd 3 8 out 7 out 6 chrin tdfn2x2-8 (top view) ep ep = exposed pad (connected to ground plane for better heat dissipation) acin chrin vbat gnd apl3215/a li+ battery gatdrv out pmic vbat gatdrv chrin isens 5v adapter or usb
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v acin aci n input voltage ( acin to gnd) - 0.3 ~ 20 v v chrin chrin to gnd voltage - 0.3 ~ 7 v v gatdrv gatdrv to gnd voltage - 0.3 ~ v chrin v v bat vbat to gnd voltage - 0.3 ~ 7 v v out out to gnd voltage - 0.3 ~ 7 v i out out outp ut current 1.5 a t j maximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature , 10 seconds 26 0 o c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol parameter typical value unit q ja junction - to - ambient resistance in free air (note 2) tdfn2x2 - 8 75 o c/w t h e r m a l c h a r a c t e r i s t i c note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of tdfn2x2-8 is soldered directly on the pcb. n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . apl3215 apl3215a package code operating ambient temperature range i : -40 to 85 o c handling code tr : tape & reel assembly material handling code temperature range package code x - date code g : halogen and lead free device assembly material qb : tdfn2x2-8 apl 3215 qb: l15 x x - date code apl 3215a qb: l15a x
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 3 symbol parameter range unit v acin acin input voltage 4.5 ~ 5.5 v i out output current 0 ~ 700 ma t a ambient temperature - 40 ~ 85 o c t j junction temperature - 40 ~ 125 o c unless otherwise specified, these specifications apply over v acin =5v, v bat =3.8v and t a = -40 ~ 85 o c. typical values are at t a =25 o c. ap l3215/a symbol parameter test conditions min . typ . max . unit acin input current and power - on - reset (por) i acin acin supply current i out =0a, i chrin =0a, t a =25 o c - 250 350 m a v acin acin por threshold 2.4 - 2.8 v acin por hysteresis 200 275 350 m v t b(acin) acin power - on blanking time - 8 - ms internal switch on resistance acin to out on resistance i out =0.7a - 0.5 - w chrin discharge on resistance - 500 - w input over - voltage protection (ovp) apl3215 6 6.17 6.35 v ovp input ovp threshold v acin rising apl3215a 6.6 6.8 7 v input ovp hysteresis 200 300 400 mv input ovp propagation delay - - 1 m s t on(ovp) input ovp recovery time - 8 - ms over - current protection (ocp) i ocp ocp threshold t a =25 o c 1 1.5 - a t b(ocp) ocp blanking time - 176 - m s t on(ocp) ocp recovery time - 64 - ms battery over - voltage protection v bovp battery ovp threshold v bat rising 4.32 4.35 4.38 v battery ovp hysteresis 220 270 320 mv i vbat vbat pin leakage current v bat = 4.4v - - 20 na t b(bovp) battery ovp blanking time - 176 - m s chrin, out and gatdrv v chrin from low to high, p - mosfet is con trolled by gatdrv - 150 - v chrin - v bat lockout threshold v chrin from high to low, p - mosfet is off - 20 - mv out input current v chrin =0v, v out =4.2v, v gatdrv =0v - - 1 m a gatdrv leakage current v acin =v chrin = v out =5v, v gatdrv =0v - - 1 m a out leakage current v acin =v chrin = v gatdrv = 5v, v out =0v - - 1 m a e l e c t r i c a l c h a r a c t e r i s t i c s r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) note 3: refer to the typical application circuit
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 4 apl3215/a symbol parameter test conditions min. typ. max. unit chrin, out and gatdrv (cont.) p - mosfet input capacitance - 200 - pf gatdrv gate resistance - 15 - w p - mosfet gate threshold voltage i out =0.7a - 1. 8 - v thermal shutdown protectio n t otp thermal shutdown threshold - 160 - o c thermal shutdown hysteresis - 40 - o c unless otherwise specified, these specifications apply over v acin =5v, v bat =3.8v and t a = -40 ~ 85 o c. typical values are at t a =25 o c. e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 5 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s o c p t h r e s h o l d , i o c p ( a ) junction temperature ( ) o c ocp threshold vs . junction temperature 1 . 00 1 . 05 1 . 10 1 . 15 1 . 20 1 . 25 1 . 30 1 . 35 1 . 40 1 . 45 1 . 50 1 . 55 - 50 - 25 0 25 50 75 100 125 acin supply current, i acin ( m a) acin supply current vs . junction temperature junction temperature ( o c ) - 50 - 25 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 p o w e r s w i t c h o n r e s i s t a n c e , r d s , o n ( m w ) junction temperature ( o c ) power switch on resistance vs . junction temperature 300 400 500 600 700 800 - 50 - 25 0 25 50 75 100 125 acin to out on resistance ) o c i n p u t o v p t h r e s h o l d , v o v p ( v ) junction temperature ( input ovp threshold vs . junction temperature - 50 - 25 0 25 50 75 100 125 6 . 2 6 . 3 6 . 4 6 . 5 6 . 6 6 . 7 6 . 8 6 . 9 7 . 0 v acin increasing v acin decreasing apl 3215 a battery ovp threshold vs . junction temperature b a t t e r y o v p t h r e s h o l d , v b o v p ( v ) junction temperature ( o c ) - 50 - 25 0 25 50 75 100 125 4 . 00 4 . 05 4 . 10 4 . 15 4 . 20 4 . 25 4 . 30 4 . 35 4 . 40 v bat increasing v bat decreasing p o r t h r e s h o l d , v p o r ( v ) por threshold vs . junction temperature junction temperature ( o c ) - 50 - 25 0 25 50 75 100 125 2 . 0 2 . 1 2 . 2 2 . 3 2 . 4 2 . 5 2 . 6 2 . 7 2 . 8 v acin increasing v acin decreasing
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 6 o p e r a t i n g w a v e f o r m s t h e t e s t c o n d i t i o n i s v a c i n = 5 v , v b a t = 3 . 8 v , c a c i n = 1 m f , c c h r i n = 1 m f , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . normal power on ch 1 : v acin , 5 v / div , dc ch 2 : v out , 2 v / div , dc time : 2 m s / div v gatdrv = v chrin ch 4 : i out , 0 . 2 a / div , dc ch 3 : v chrin , 2 v / div , dc 1 2 , 3 4 v acin v out i out v chrin ovp at power on ch 1 : v acin , 10 v / div , dc ch 2 : v chrin , 2 v / div , dc v acin = 0 to 12 v , v gatdrv = v chrin ch 3 : v out , 2 v / div , dc time : 2 ms / div 1 2 3 v out v chrin v acin input over - voltage pretection v acin 1 v chrin 2 i out 3 ch 1 : v acin , 5 v / div , dc ch 2 : v chrin , 2 v / div , dc time : 5 m s / div v acin = 5 v to 12 v , r out = 50 w ch 3 : i out , 100 ma / div , dc apl 3215 a recovery from input ovp v chrin v acin 1 2 i out 3 ch 1 : v acin , 5 v / div , dc ch 2 : v chrin , 2 v / div , dc time : 2 ms / div v acin = 12 v to 5 v , r out = 50 w ch 3 : i out , 100 ma / div , dc apl 3215 a
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s ( c o n t . ) t h e t e s t c o n d i t i o n i s v a c i n = 5 v , v b a t = 3 . 8 v , c a c i n = 1 m f , c c h r i n = 1 m f , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . battery over - voltage protection v chrin v bat 1 2 ch 1 : v bat , 2 v / div , ac ch 2 : v chrin , 2 v / div , dc time : 50 ms / div v bat = 3 . 6 v to 4 . 4 v to 3 . 6 v battery over - voltage protection 1 2 v bat v chrin ch 1 : v bat , 2 v / div , dc ch 2 : v chrin , 2 v / div , dc time : 200 m s / div v bat = 3 . 6 v to 4 . 4 v over - current protection i out v chrin v acin v out ch 2 : v chrin , 5 v / div , dc ch 3 : v out , 5 v / div , dc time : 200 m s / div ch 4 : i out , 1 a / div , dc r out = 2 . 5 w , v bat = 0 v , v gatdrv = 0 v ch 1 : v acin , 5 v / div , dc 1 2 3 note : out pin connected with a resistor to ground . over - current pretection ch 1 : v chrin , 2 v / div , dc ch 2 : v out , 2 v / div , dc time : 50 m s / div ch 3 : i out , 0 . 5 a / div , dc i out = 0 a to 1 . 3 a , v bat = 0 v , v gatdrv = 0 v note : out pin connected with a resistor to ground . 3 2 1 i out v out v chrin
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 8 pin no. name f unction 1,2 acin power supply input. c onnect this pin to external dc supply. bypass to gnd with a 1 m f ( minimum ) ceramic capacitor . 3 gnd ground terminal . 4 vbat battery v oltage s ense i nput. connect this pin to pack positive terminal thro ugh a resistor . 5 gatdrv internal p - mosfet gate input. 6 chrin output pin. this pin provide s supply voltage to the pmic input. bypass to gnd with a 1 m f ( minimum ) ceramic capacitor . 7,8 out output pins. these pins provide supply source current in series with a resistor to battery. - ep exposed thermal pad. must be electrically connected to the gnd pin. b l o c k d i a g r a m p i n d e s c r i p t i o n gate driver and control logic por acin vbat out charge pump 0 . 5 v acin ovp ocp chrin gatdrv gnd thermal shutdown 1 v vbat ovp
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 9 t y p i c a l a p p l i c a t i o n c i r c u i t designation description c acin 1 m f, 25 v, x 5 r, 0 6 0 3 murata grm 188 r 6 1 e 105k c chrin 1 m f, 1 0v, x 5 r, 0 6 0 3 murata grm 188 r 6 1 a 105k murata website: www.murata.com acin chrin vbat gnd apl3215/a li+ battery gatdrv out 5v adapter/usb 0.2 w 1, 2 3 4 5 6 7, 8 c acin 1 m f c chrin 1 m f r bat 200k w pmic vbat gatdrv chrin isens
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 0 f u n c t i o n d e s c r i p t i o n acin power-on-reset (por) the apl3215/a has a built-in power-on-reset circuit to keep the output shutting off until internal circuitry is oper- ating properly. the por circuit has hysteresis and a de- glitch feature so that it will typically ignore undershoot transients on the input. when the input voltage exceeds the por threshold and after 8ms blanking time, the out- put voltage starts a soft-start to reduce the inrush current. acin over-voltage protection (ovp) the input voltage is monitored by the internal ovp circuit. when the input voltage rises above the input ovp threshold, the internal fet will be turned off within 1 m s to protect connected system on out pin. when the input voltage returns below the input ovp threshold minus the hysteresis, the fet is turned on again after 8ms recovery time. the input ovp circuit has a 300mv hysteresis and a recovery time of t on(ovp) to provide noise immunity against transient conditions. over-current protection (ocp) the output current is monitored by the internal ocp circuit. when the output current reaches the ocp threshold, the device limits the output current at ocp threshold level. if the ocp condition continues for a blanking time of t b(ocp) , the internal power fet is turned off. after the recovery time of t on(ocp) , the fet will be turned on again. the apl3215/a has a built-in counter. when the total count of ocp fault reaches 16, the fet is turned off permanently, requiring a v acin por again to restart. battery over-voltage protection the apl3215/a monitors the vbat pin voltage for battery over-voltage protection. the battery ovp threshold is in- ternally set to 4.35v. when the vbat pin voltage exceeds the battery ovp threshold for a blanking time of t b(bovp) , the internal power fet is turned off. when the vbat volt- age returns below the battery ovp threshold minus the hysteresis, the fet is turned on again. the apl3215/a has a built-in counter. when the total count of battery ovp fault reaches 16, the fet is turned off permanently, re- quiring a v acin por again to restart. over-temperature protection when the junction temperature exceeds 160 o c, the inter- nal thermal sense circuit turns off the power fet and allows the device to cool down. when the device?s junc- tion temperature cools by 40 o c, the internal thermal sense circuit will enable the device, resulting in a pulsed output during continuous thermal protection. thermal pro- tection is designed to protect the ic in the event of over- temperature conditions. for normal operation, the junc- tion temperature cannot exceed t j =+125 o c. internal p-mosfet the apl3215/a integrates a p-channel mosfet with the body diode reverse protection to replace the external p- mosfet and schottky diode for cell phone?s pmic. the body diode reverse protection prevents a reverse current flowing from the battery back to chrin pin. during power- on, when chrin voltage rises above the vbat voltage by more than 150mv, the body diode of the p-channel mosfet is forward biased from out to chrin, and p- mosfet is controlled by the external gatdrv voltage. when the chrin voltage drops below v bat +20mv, the body diode of the p-channel mosfet is forward biased from chrin to out and p-channel mosfet is turned off. when any of input ovp, ocp, battery ovp, is detected, the internal p-channel mosfet is also turned off. t h e a p l 3 2 1 5 / a v i n i n p u t p i n f u l l y s u p p o r t s t h e i e c 6 1 0 0 0 - 4 - 2 . t h a t m e a n s t h e v i n p i n h a s i m m u n i t y o f 1 5 k v e s d d i s c h a r g e i n a i r c o n d i t i o n , a n d i m m u n i t y o f 8 k v e s d d i s c h a r g e i n c o n t a c t c o n d i t i o n . e s d t e s t s
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 1 f u n c t i o n d e s c r i p t i o n ( c o n t . ) figure 1. ovp timing diagram v por v ovp v acin acin ovp t on(ovp) v chrin v chrin -v bat = 150mv t b( acin) p-mos gate control v out turn off internal p-mosfet contro l l ed by gatdrv v chrin -v bat = 150mv turn off internal p-mosfet gatdrv is pulled low contro l l ed by gatdrv figure 2. ocp timing diagram count 13 times i out total count 16 times, ic is latched off v chrin t b(ocp) t on( ocp) p-mos gate control t b(ocp) t b(ocp) turn off internal p-mosfet turn off internal p- mosfet turn off internal p- mosfet i ocp gatdrv is pulled low control l ed by gatdrv control l ed by gatdrv contro l l ed by gatdrv
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 2 f u n c t i o n d e s c r i p t i o n ( c o n t . ) figure 3. battery ovp timing diagram v chrin count 13 times v bat t b( b ovp) total count 16 times, ic is latched off p-mos gate control v bovp t b( b ovp) v bovp v chrin -v out = 150mv t b( b ovp) turn off internal p-mosfet turn off internal p-mosfet turn off internal p- mosfet contro l l ed by gatdrv control l ed by gatdrv control l ed by gatdrv
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 3 a p p l i c a t i o n i n f o r m a t i o n r b a t s e l e c t i o n connect the vbat pin to the positive terminal of battery through a resistor r bat for battery ovp function. the r bat limits the current flowing from vbat to battery in case of vbat pin is shortened to acin pin under a failure mode. the recommended value of r bat is 200k w . in the worse case of an ic failure, the current flowing from the vbat pin to the battery is: (20v-3v) / 200k w =85 m a where the 20v is the maximum acin voltage and the 3v is the minimum battery voltage. the current is so small and can be absorbed by the charger system. capacitor selection the input capacitor is for decoupling and prevents the input voltage from overshooting to dangerous levels. in the ac adapter hot plug-in applications or load current step-down transient, the input voltage has a transient spike due to the parasitic inductance of the input cable. a 25v, x5r, dielectric ceramic capacitor with a value be- tween 1 m f and 4.7 m f placed close to the acin pin is recommended. the output capacitor of chrin is for chrin voltage decoupling. also, it can be as the input capacitor of the charging circuit. at least, a 1 m f, 10v, x5r capacitor is recommended. layout consideration in some failure modes, a high voltage may be applied to the device. make sure the clearance constraint of the pcb layout must satisfy the design rule for high voltage. the exposed pad of the tdfn2x2-8 performs the function of channeling heat away. it is recommended that connect the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias to improve heat dissipation. the input and output capaci- tors should be placed close to the ic. the high current traces like input trace and output trace must be wide and short. thermal considerations the maximum power dissipation depends on the ther- mal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by the following formula: p d(max) = (t j(max) -t a ) / q ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the q ja is the junction to ambient thermal resistance. for recom- mended operating conditions specification of apl3215/a, where t j(max) is 125 o c and t a is the operated ambient temperature. the junction to ambient thermal resistance q ja for tdfn2x2-8 package is 75 o c/w on a high effective thermal conductivity test board in free air. the maximum power dissipation at t a = 25 o c can be calculated by the following formula : p d(max) = (125 o c-25 o c) / (75 o c/w) = 1.33w for tdfn2x2-8 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resis- tance q ja . for apl3215/a packages, the figure 4 of derat- ing curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. f i g u r e 4 . d e r a t i n g c u r v e s f o r a p l 3 2 1 5 / a p a c k a g e s p o w e r d i s s i p a t i o n ( w ) ambient temperature ( o c ) 1 . 0 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 2 1 . 4 1 . 6 0 25 50 75 100 125 tdfn 2 x 2 - 8
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 4 p a c k a g e i n f o r m a t i o n t d f n 2 x 2 - 8 s y m b o l min. max. 0.80 0.00 0.18 0.30 1.00 1.60 0.05 0.60 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tdfn2x2-8 0.30 0.45 1.00 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.039 0.063 0.024 0.012 0.018 0.70 0.039 0.028 0.002 0.50 bsc 0.020 bsc 1.90 2.10 0.075 0.083 1.90 2.10 0.075 0.083 k 0.20 0.008 note : 1. followed from jedec mo-229 wccd-3. e l k e 2 pin 1 corner d2 a3 a1 b a e d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 5 application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 8.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 8.0 ? 0.20 1.75 ? 0.10 3.50 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn2x2 - 8 4.0 ? 0.10 4.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0 .4 3.35 min 3.35 min 1.30 ? 0.20 (mm) d e v i c e s p e r u n i t package type unit quantity tdfn2x2 - 8 tape & reel 3000 c a r r i e r t a p e & r e e l d i m e n s i o n s h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 6 t a p i n g d i r e c t i o n i n f o r m a t i o n t d f n 2 x 2 - 8 user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 7 profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spe cified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. c l a s s i f i c a t i o n p r o f i l e c l a s s i f i c a t i o n r e f l o w p r o f i l e s
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - s e p . , 2 0 1 1 a p l 3 2 1 5 / a w w w . a n p e c . c o m . t w 1 8 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 c l a s s i f i c a t i o n r e f l o w p r o f i l e s ( c o n t . ) table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c r e l i a b i l i t y t e s t p r o g r a m test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ tj=125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma

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